The present invention relates generally to digital data processing equipment and more specifically to an improvement to computer input/output (I/O) hardware.
A major innovation in computer I/O art was the implementation of asynchronous, buffered I/O transfers. This capability permits multiple byte and word I/O transfers to occur asynchronously to and without intervention by the computer programs being executed. It is recommended that the reader review the operation of asynchronous, buffered I/O transfers as taught by R. L. Burkholder, et al, in U.S. Pat. No. 3,251,040.
A second major innovation was the use of a single I/O channel to communicate with multiple peripheral devices. Though many techniques have been implemented to accomplish this, the technique most often referred to herein is called Externally Specified Indexing (ESI). ESI permits multiple peripheral device usage of a single I/O channel employing asynchronous, buffered I/O transfers by maintaining multiple buffer control words (BCW's). Each one of the multiple peripheral devices on a single I/O channel has one dedicated BCW to maintain the status of and control the I/O transfers with that one of the multiple peripheral devices. Each one of the multiple peripheral devices transfers an index uniquely identifying itself to enable the computer to select the corresponing BCW to properly control each data transfer. For a detailed description of ESI operation, the reader is urged to review the technique as taught by C. W. Ehrman, et al, in U.S. Pat. No. 3,243,781.
ESI as taught by the Ehrman Patent utilizes BCW's stored in the computer's main memory. This provides each I/O channel with storage space for as many BCW's as needed. Storing BCW's in main memory has the disadvantage of requiring a relatively slow main memory reference to access a BCW, however. Therefore, as componently advanced, ESI was improved by storing BCW's in a relatively small but fast random access memory (RAM) of semiconductor construction, called ICU General Registers (IGR). Each individual addressable location within the IGR is dedicated to storage of the BCW for that one peripheral device transferring the corresponding index uniquely identifying it. A single addressable location of the IGR, along with the other hardware unique to communication with a single peripheral device is called an I/O subchannel. Because of the cost of the hardware, the total number of I/O subchannels tends to be limited. Therefore, the total number of peripheral devices that may be connected in the ESI mode is limited to some number thought to provide sufficient flexibility and yet be economically feasible. Furthermore, prior systems have allocated a fixed number of I/O subchannels to each I/O channel employing the ESI mode. This allocation method is easily accomplished. However, maximum flexibility is not achieved because each I/O channel is limited in total I/O transfer bandwidth as well as number of I/O subchannels. The result for many configurations is that some I/O channels are I/O transfer bandwidth limited without utilizing all available I/O subchannels whereas other I/O channels are limited by the number of I/O subchannels available while remaining within the total I/O bandwidth of the I/O channel. This situation may make the number of usable I/O subchannels less than the number physically present in the hardware.
The present invention overcomes this deficiency by permitting flexibility in the allocation of I/O subchannels to I/O channels.